淡江大學機構典藏:Item 987654321/50572
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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/50572


    Title: Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique
    Authors: Lo, Yu-lung;Yang, Wei-bin;Chao, Ting-sheng;Cheng, Kuo-hsing
    Contributors: 淡江大學電機工程學系
    Keywords: Bulk driven;forward body bias (FBB);phase-locked loop (PLL);ultralow voltage;voltage-controlled oscillator (VCO)
    Date: 2009-05-01
    Issue Date: 2010-08-09 19:54:37 (UTC+8)
    Publisher: Piscataway: Institute of Electrical and Electronics Engineers
    Abstract: This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13-mum standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 mm2.
    Relation: IEEE Transactions on Circuits and Systems II: Express Briefs 56(5), pp.339-343
    DOI: 10.1109/TCSII.2009.2019160
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

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