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    題名: Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique
    作者: Lo, Yu-lung;Yang, Wei-bin;Chao, Ting-sheng;Cheng, Kuo-hsing
    貢獻者: 淡江大學電機工程學系
    關鍵詞: Bulk driven;forward body bias (FBB);phase-locked loop (PLL);ultralow voltage;voltage-controlled oscillator (VCO)
    日期: 2009-05-01
    上傳時間: 2010-08-09 19:54:37 (UTC+8)
    出版者: Piscataway: Institute of Electrical and Electronics Engineers
    摘要: This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13-mum standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 mm2.
    關聯: IEEE Transactions on Circuits and Systems II: Express Briefs 56(5), pp.339-343
    DOI: 10.1109/TCSII.2009.2019160
    顯示於類別:[電機工程學系暨研究所] 期刊論文


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