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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/50557

    Title: Low-power/High-speed scalable and subchannelizable FFT architecture for SOFDMA application
    Authors: 李揚漢;Lee, Yang-han;Chiang, Jen-shiun;Chou, Yen-hsih;Lee, Yu-shih;Tseng, Hsien-wei;Chuang, Ming-hsueh
    Contributors: 淡江大學電機工程學系
    Keywords: FFT;SOFDMA;WiMAX, SELDIF;Scalable;Subchannelizable
    Date: 2008-09-01
    Issue Date: 2010-08-09 19:47:51 (UTC+8)
    Publisher: 淡江大學
    Abstract: In this paper, a scalable and subchannelizable innovative FFT architecture is proposed to provide with low-power and high-speed characteristics for SOFDMA application in IEEE 802.16 WiMAX communication and other fields that have features in SOFDMAapplications. The scalability design uses multiplexing concept to build only one 1024-point and only one 2048-point FFT processors in an IEEE 802.16e and an IEEE 802.16-2004 WiMAX system respectively. The spirits of
    the subchannelization design are prohibited all of the unused arithmetic operations in the present inventive design to achieve low-power requirement when only a small subset of FFT outputs are of interests for a specific Subscriber Station in one session of a IEEE 802.16e or IEEE 802.16-2004 WiMAX systems. The SELDIF registry control methodology of the key control mechanism of the subchannelization design is also disclosed for the purposes of structure simplification and low-power/high-speed design in this paper. The performance on areas and power efficiency are analyzed based on MATLAB codes. A closed system platform is used to tune design parameters for chip implementation by using Agilent ADS tool.
    Relation: 淡江理工學刊 = Tamkang Journal of Science and Engineering 11(3), pp.313-324
    DOI: 10.6180/jase.2008.11.3.10
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

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