The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. However, its computation is so intensive and it is important to meet the requirement for high speed. A novel architecture of the VLSI design of a 2D DCT has been developed. This architecture contains the following features: use of the programmable logic array (PLA) to replace multipliers; overlapped row–column operations and pipeline structure to reduce the total computation time; and highly modular and regular structure for the efficient VLSI implementation. This architecture is implemented to a 8 × 8 2D DCT. The circuit is designed by UMC's 0.8 μm SPDM CMOS process and the cell library is provided by ITRI CCL. The simulation is shown that the speed of the data processing for this DCT is more than 50 MHz. It performs equivalently 800 million multiplications and accumulations per second.
Relation:
International journal of electronics 83(4), pp.519-527
