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    題名: The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock
    作者: 江正雄;Chiang, Jen-shiun;Chen, Kuang-yuan
    貢獻者: 淡江大學電機工程學系
    日期: 1999-07
    上傳時間: 2010-03-26 21:36:22 (UTC+8)
    出版者: New York: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: The cores of the all-digital phase-locked loop (ADPLL) are the switch-tuning digital control oscillator (DCO) and the architecture. In this brief, we propose a DCO with reduced hardware cost, and architecture with characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high-performance microprocessors. The prototype of a 3.3-V ADPLL chip has been designed by TSMC’s 0.6-m SPDM CMOS process. The simulation shows that this ADPLL can operate in the range between 60 and 400 MHz, and at four times the reference clock frequency. The phase-lock process takes 47 clock cycles, and the phase error is less than 0.1 ns.
    關聯: IEEE Transactions on Circuits and Systems Part 2: Analog and Digital Signal Processing 46(7), pp.945-950
    DOI: 10.1109/82.775392
    顯示於類別:[電機工程學系暨研究所] 期刊論文

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