A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps

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Title:	A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps
Authors:	郭建宏;Kuo, Chien-hung;Liu, Shen-iuan
Contributors:	淡江大學電機工程學系
Date:	2004-11
Issue Date:	2010-03-26 21:11:52 (UTC+8)
Publisher:	Piscataway: Institute of Electrical and Electronics Engineers (IEEE)
Abstract:	A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-μm 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.
Relation:	IEEE Journal of Solid-State Circuits 39(11), pp.2041-2045
DOI:	10.1109/JSSC.2004.835792
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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