Dynamic Bias Circuits for Efficiency Improvement of RF Power Amplifier

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Journal Article > Item 987654321/46134

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Title:	Dynamic Bias Circuits for Efficiency Improvement of RF Power Amplifier
Authors:	余繁;Ye, Fun;Chiang, Jen-shiun;Chen, Chun-wen;Sung, Yu-chen
Contributors:	淡江大學電機工程學系
Keywords:	CMOS;Dynamic Bias Circuits;Linearity;Power Added Efficiency;Power Amplifie;RF
Date:	2004-09-01
Issue Date:	2010-03-26 21:02:27 (UTC+8)
Publisher:	淡江大學
Abstract:	This work presents a dynamic gate bias circuit for bias control to maximize power added efficiency based on the class-A two-stage power amplifier. The proposed circuits are composed of two NMOS transistors, a capacitor for coupling RF input signal, and four resistors for bias. The circuit is implemented by means of the bias control at the two-stage power amplifier to improve the overall power added efficiency and delivers 22dBm output power at 2.4 GHz. The circuit can improve power efficiency and linearity for small RF signals. The simulation indicates that the efficiency is improved more than 100%, and at 0 dBm the input signal has 5-15dB of IMD3 improvement compared with that without dynamic bias circuit. The output power of 22dBm at the output stage can be applied to the transceivers of IEEE 802.11b and Bluetooth applications.
Relation:	淡江理工學刊=Tamkang journal of science and engineering 7(3), pp.183-188
DOI:	10.6180/jase.2004.7.3.09
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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