A Novel Architecture for High-Speed Viterbi Decoder

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/46127

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题名:	A Novel Architecture for High-Speed Viterbi Decoder
作者:	李揚漢;Lee, Yang-han;詹益光;Jan, Yih-guang;Tseng, Hsien-wei;Chuang, Ming-hsueh;Peng, Chiung-hsuan;李維聰;Lee, Wei-tsong;Chen, Chih-tsung
贡献者:	淡江大學電機工程學系
关键词:	Viterbi Decoder;Add-Compare-Select Unit ACSU;Cyclic-Shift Register Unit CSRU;Pseudo-Correlator Unit PCU
日期:	2006-12
上传时间:	2010-03-26 21:00:27 (UTC+8)
出版者:	淡江大學
摘要:	In this paper we present a high-speed and low-complexity Viterbi decoder architecture. The Add-Compare-Select Unit (ACSU) is an indispensable unit in the Viterbi decoder. The processing speed in the conventional architecture of Viterbi decoder is limited due to the large amounts of calculations executed in the ACSU. Meanwhile in the hardware implementation of the ACSU it also encounters a great extent of wires connecting complexities. We propose to create the Cyclic-Shift Register Unit (CSRU) and the Pseudo-Correlator Unit (PCU) in the ACSU so that ultimately it not only reduces its hardware connecting complexities in the unit but also improves the overall processing speed in the Viterbi decoder. We make analysis and comparison in the hardware complexities and processing speed between our proposed and conventional architectures in the Viterbi decoder.
關聯:	淡江理工學刊=Tamkang journal of science and engineering 9(4), pp.343-352
DOI:	10.6180/jase.2006.9.4.06
显示于类别:	[電機工程學系暨研究所] 期刊論文

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