A Novel Architecture for High-Speed Viterbi Decoder

doi:10.6180/jase.2006.9.4.06

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Journal Article > Item 987654321/46127

Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/46127

Title:	A Novel Architecture for High-Speed Viterbi Decoder
Authors:	李揚漢;Lee, Yang-han;詹益光;Jan, Yih-guang;Tseng, Hsien-wei;Chuang, Ming-hsueh;Peng, Chiung-hsuan;李維聰;Lee, Wei-tsong;Chen, Chih-tsung
Contributors:	淡江大學電機工程學系
Keywords:	Viterbi Decoder;Add-Compare-Select Unit ACSU;Cyclic-Shift Register Unit CSRU;Pseudo-Correlator Unit PCU
Date:	2006-12
Issue Date:	2010-03-26 21:00:27 (UTC+8)
Publisher:	淡江大學
Abstract:	In this paper we present a high-speed and low-complexity Viterbi decoder architecture. The Add-Compare-Select Unit (ACSU) is an indispensable unit in the Viterbi decoder. The processing speed in the conventional architecture of Viterbi decoder is limited due to the large amounts of calculations executed in the ACSU. Meanwhile in the hardware implementation of the ACSU it also encounters a great extent of wires connecting complexities. We propose to create the Cyclic-Shift Register Unit (CSRU) and the Pseudo-Correlator Unit (PCU) in the ACSU so that ultimately it not only reduces its hardware connecting complexities in the unit but also improves the overall processing speed in the Viterbi decoder. We make analysis and comparison in the hardware complexities and processing speed between our proposed and conventional architectures in the Viterbi decoder.
Relation:	淡江理工學刊=Tamkang journal of science and engineering 9(4), pp.343-352
DOI:	10.6180/jase.2006.9.4.06
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

Files in This Item:

File	Size	Format
index.html	0Kb	HTML	426	View/Open

Loading...