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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/46094

    Title: 局部非同步邏輯電路的真單相位時脈架構
    Authors: 黃弘一;鄭國興;吳重雨
    Contributors: 淡江大學電機工程學系
    Keywords: 真單相位時脈;非同步邏輯電路;差動邏輯;鎖定器;預置;取值 True-single-phase clock;Asynchronous logic circuit;Differential logic;Latch;Precharge;Evaluate
    Date: 1995-09
    Issue Date: 2013-03-12 13:31:16 (UTC+8)
    Publisher: 新竹縣:工業技術研究院 電腦與通訊工業研究所
    Relation: 電腦與通訊=CCL Technical Journal 42,頁63-70
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

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