VSTA : a prolog-based formal verifier for systolic array designs

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Title:	VSTA : a prolog-based formal verifier for systolic array designs
Authors:	Ling, Nam;施國琛;Shih, Timothy K.
Contributors:	淡江大學資訊工程學系
Date:	1993-08
Issue Date:	2010-03-26 19:40:30 (UTC+8)
Publisher:	CRC press
Relation:	Proceedings of the 1993 International Conference on Parallel Processing 2, pp.73-81
Appears in Collections:	[Graduate Institute & Department of Computer Science and Information Engineering] Proceeding

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