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    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/45442

    Title: On the construction of a prolog-based verifier for systolic array designs
    Authors: 施國琛;Shih, Timothy K.;Ling, Nam;Davis, Ruth;Lin, Fuyau
    Contributors: 淡江大學資訊工程學系
    Date: 1995-02-01
    Issue Date: 2010-03-26 19:20:27 (UTC+8)
    Publisher: Wiley-Blackwell
    Relation: Computational intelligence 11(1), pp.172-221
    DOI: 10.1111/j.1467-8640.1995.tb00027.x
    Appears in Collections:[Graduate Institute & Department of Computer Science and Information Engineering] Journal Article

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