Effect of Sampling Time Jitter on Array Performance

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題名:	Effect of Sampling Time Jitter on Array Performance
作者:	Baker, Charles R.;趙榮耀;Chow, Louis R.
貢獻者:	淡江大學資訊工程學系
日期:	1978-09
上傳時間:	2010-03-26 19:06:12 (UTC+8)
出版者:	Piscataway: Institute of Electrical and Electronics Engineers (IEEE)
摘要:	The effect on array SNR of errors in sampling times (jitter) isan analyzed for the "Bryn processor." Jitter is modeled as a discrete-paramter er random process, and expressions for array SNR are determined as a function of signal and noise spectra and jitter characteristics. For a plane wave signal, it is found that jitter in the data used to design the processor has no effect on output SNR if the noise is independent between channels. However, jitter in the input (evaluation) n) data can cause a substantial loss in peak array SNR and in the array's frequency selectivity. These losses can be expected to increase as the high-frequency content of the data increases. The Bryn processor also loses its interpretation as a likelihood ratio processor in the presence of jitter. The effect of jitter can be reduced in many cases by increasing the sampling rate.
關聯:	IEEE transaction on Aerospace and Electronic Systems Aes-14(5), pp.780-788
DOI:	10.1109/TAES.1978.308629
顯示於類別:	[資訊工程學系暨研究所] 期刊論文

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