Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/39059

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題名:	Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit
作者:	Tseng, Yuh-kuang;鄭國興;Cheng, Kuo-hsing;Wu, Chung-yu
貢獻者:	淡江大學電機工程學系
日期:	1994-05-30
上傳時間:	2010-04-15 10:55:36 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	This paper describes a new feedback-controlled enhanced-pull-down BiCMOS (FC-EPD-BiCMOS) logic scheme for the low-supply-voltage operation. Through the use of the feedback-controlled enhanced-pull-down structure, the driving capability is improved and bipolar transistor saturation during operation period is avoided. Based upon the proposed. Structure, both static and differential logic gates are developed. The new BiCMOS three-input NAND gate offers 35% reduction in the propagation delay time as compared to conventional BiCMOS circuits at 2.5 V supply voltage. The proposed three-input FC-EPD-BiCMOS CPL XOR/XNOR gate has 33% improvement in delay time as compared to conventional BiCMOS 3-input XOR/XNOR gates at 2.4 V supply voltage.
關聯:	Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, vol.4, pp.23-26
DOI:	10.1109/ISCAS.1994.409187
顯示於類別:	[電機工程學系暨研究所] 會議論文

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