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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/39059


    Title: Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit
    Authors: Tseng, Yuh-kuang;鄭國興;Cheng, Kuo-hsing;Wu, Chung-yu
    Contributors: 淡江大學電機工程學系
    Date: 1994-05-30
    Issue Date: 2010-04-15 10:55:36 (UTC+8)
    Publisher: Institute of Electrical and Electronics Engineers (IEEE)
    Abstract: This paper describes a new feedback-controlled enhanced-pull-down BiCMOS (FC-EPD-BiCMOS) logic scheme for the low-supply-voltage operation. Through the use of the feedback-controlled enhanced-pull-down structure, the driving capability is improved and bipolar transistor saturation during operation period is avoided. Based upon the proposed. Structure, both static and differential logic gates are developed. The new BiCMOS three-input NAND gate offers 35% reduction in the propagation delay time as compared to conventional BiCMOS circuits at 2.5 V supply voltage. The proposed three-input FC-EPD-BiCMOS CPL XOR/XNOR gate has 33% improvement in delay time as compared to conventional BiCMOS 3-input XOR/XNOR gates at 2.4 V supply voltage.
    Relation: Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, vol.4, pp.23-26
    DOI: 10.1109/ISCAS.1994.409187
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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