A novel reseeding mechanism for pseudo-random testing of VLSI circuits

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Title:	A novel reseeding mechanism for pseudo-random testing of VLSI circuits
Authors:	Rau, Jiann-chyi;Ho, Ying-fu;Wu, Po-han
Contributors:	淡江大學電機工程學系
Date:	2005-05-23
Issue Date:	2010-04-15 11:13:34 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers (IEEE)
Abstract:	During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault (useless patterns). In order to reduce the test time, we can remove useless patterns or change them to useful patterns (fault dropping). In this paper, we reseed, modify the pseudo-random, and use an additional bit counter to improve test length and achieve high fault coverage. The fact is that a random test set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change them to useful patterns, and when the patterns change, we pick out the numbers with less bits, leading to very short test length. The technique we present is applicable for single-stuck-at faults. The seeds we use are deterministic so 100% fault coverage can be achieve.
Relation:	Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (Volume:3 ), pp.2979-2982
DOI:	10.1109/ISCAS.2005.1465253
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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