Reconfigurable multiple scan-chains for reducing test application time of SOCs

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/39042

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题名:	Reconfigurable multiple scan-chains for reducing test application time of SOCs
作者:	Rau, Jiann-chyi;Chien, Chih-lung;Ma, Jia-shing
贡献者:	淡江大學電機工程學系
日期:	2005-05-23
上传时间:	2010-04-15 11:13:00 (UTC+8)
出版者:	N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
摘要:	We propose an algorithm, based on a framework of reconfigurable multiple scan-chains for a system-on-chip, to minimize test application time. For the framework, the control signal combination causes the computing time to increase exponentially. The algorithm we propose introduces a heuristic control signal selection method to solve this problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan-chains. It could show significant reductions in test application times and computing times.
關聯:	Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (Volume:6 ), pp.5846-5849
DOI:	10.1109/ISCAS.2005.1465968
显示于类别:	[電機工程學系暨研究所] 會議論文

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