N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
We propose an algorithm, based on a framework of reconfigurable multiple scan-chains for a system-on-chip, to minimize test application time. For the framework, the control signal combination causes the computing time to increase exponentially. The algorithm we propose introduces a heuristic control signal selection method to solve this problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan-chains. It could show significant reductions in test application times and computing times.
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (Volume:6 ), pp.5846-5849