淡江大學機構典藏:Item 987654321/39041
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    題名: An efficient mechanism for debugging RTL description
    作者: Ran, Jiann-chyi;Chang, Yi-yuan;Lin, Chia-hung
    貢獻者: 淡江大學電機工程學系
    日期: 2003-06-30
    上傳時間: 2010-04-15 10:55:19 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: In this paper, an efficient algorithm to diagnose design errors in RTL description is proposed. The diagnosis algorithm exploits the hierarchy available in RTL designs to locate design errors. Using data-path to reduce the number of error candidates and ensure that true errors are included in. According to the estimated probability, the most suspected error candidates would be reported first in the display. The advantages of the proposed method are simple and available.
    關聯: System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on, pp.370-373
    DOI: 10.1109/IWSOC.2003.1213064
    顯示於類別:[電機工程學系暨研究所] 會議論文

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