Institute of Electrical and Electronics Engineers (IEEE)
摘要:
In this paper, we propose a novel way to build a "DC_image" circuit for the don't cares. The DC_image circuits are concatenated with the inputs of the two circuits under verification. By adding the image circuits, no matter how don't cares are in on-/off-sets, we can directly verify the two circuits with DC_image circuits and claim whether there exists an inconsistency between the original and optimized circuits. Our experimental results show that by the DC_image circuits, the verification process can be sped up tremendously.
關聯:
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on (Volume:5 ), pp.325-328
