A timing-driven pseudo-exhaustive testing of VLSI circuits

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/38935

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题名:	A timing-driven pseudo-exhaustive testing of VLSI circuits
作者:	Chang, S. C.;Rau, J. C.
贡献者:	淡江大學電機工程學系
日期:	2000-05
上传时间:	2010-04-15 11:41:05 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	The object of this paper is to reduce the delay penalty of bypass storage cell (bsc) insertion for pseudo-exhaustive testing. We first propose a tight delay lower bound algorithm which estimates the minimum circuit delay for each node after bsc insertion. By understanding how the lower bound algorithm loses optimality, we can propose a bsc insertion heuristic which tries to insert bscs so that the final delay is as close to the lower bound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.
關聯:	Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on (Volume:2 ), pp.665-668
DOI:	10.1109/ISCAS.2000.856416
显示于类别:	[電機工程學系暨研究所] 會議論文

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