Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits

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題名:	Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits
作者:	Huang, Hong-yi;鄭國興;Cheng, Kuo-hsing;Wang, Jinn-shyan;Chu, Yuan-hua;Wu, Tain-shun;Wu, Chung-yu
貢獻者:	淡江大學電機工程學系
日期:	1995-04-30
上傳時間:	2010-04-15 10:57:40 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	New CMOS differential logic circuits, called asynchronous latched CMOS differential logic (ALCDL) circuits, are proposed and analyzed. The ALCDL can implement a complex function in a single gate and achieve high operation speed without DC power dissipation. New CMOS differential latches, which can be used to prevent extra transitions and reduce the power dissipation, are also proposed. A new clocking scheme is designed by locally using the ALCDL circuits and the entire system is synchronized to a single global clock. As compared to the conventional true-single-phase clock system, the loading of the global clock line and transient noise induced by precharge operation can be largely reduced. Simulation results show that the new clocking scheme and logic circuits benefit in high-speed and low-power performances, especially in low supply voltage.
關聯:	Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on (Volume:3 ), pp.1572-1575
DOI:	10.1109/ISCAS.1995.523707
顯示於類別:	[電機工程學系暨研究所] 會議論文

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