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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38864


    Title: Low voltage low power high-speed BiCMOS multiplier
    Other Titles: 低功率低電壓高速度之雙載子金氧半電晶體乘法器
    Authors: 鄭國興;Cheng, Kuo-hsing;Yeha, Yu-kwang;Lian, Farn-sou
    Contributors: 淡江大學電機工程學系
    Date: 1998
    Issue Date: 2010-04-15 10:46:48 (UTC+8)
    Publisher: Institute of Electrical and Electronics Engineers (IEEE)
    Abstract: A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation
    Relation: Electronics, Circuits and Systems, 1998 IEEE International Conference on (Volume:2 ), pp.49-50
    DOI: 10.1109/ICECS.1998.814820
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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