Institute of Electrical and Electronics Engineers (IEEE)
Abstract:
A 16×16-bit parallel multiplier fabricated in a 1.0 μm BiCMOS technology is described. The chip uses a modified array scheme incorporated with Booth's algorithm to reduce the adding stages of partial products. The combination of CMOS and BiCMOS circuits and advanced arithmetic architecture achieve a multiplication time of 32.74 ns while dissipation only 298 μW at 2.5 V supply voltage operation
Relation:
Electronics, Circuits and Systems, 1998 IEEE International Conference on (Volume:2 ), pp.49-50