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    題名: A suggestion for low-power current-sensing complementary pass-transistor logic interconnection
    作者: 鄭國興;Cheng, Kuo-hsing;Yee, Liow-yu;Chen, Jian-hung
    貢獻者: 淡江大學電機工程學系
    日期: 1997-06-09
    上傳時間: 2010-04-15 10:56:12 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: In this paper, a new circuit interconnection scheme of the low-power current-sensing complementary pass-transistor logic (LCSCPTL) is proposed and analyzed. The proposed new circuit scheme using full-swing and non-full-swing output signals to control the NMOS pass transistor logic tree network. Due to the non-full-swing outputs and the current-sensing scheme, the new logic circuit scheme can improve the power dissipation and operation speed. The non-full-swing LCSCPTL is applied to the design of the parallel multiplier. The 4-2 compressors and the conditional carry selection scheme are used in this design to achieve regular layout and improve the operation speed. Moreover, the 1.2 V 8×8-bit parallel multiplier can be fabricated without changing the conventional 5 V CMOS process. The operation speed of the parallel multiplier is 32 ns for 1.2 V supply voltage.
    關聯: Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, vol.3, pp.1948-1951
    DOI: 10.1109/ISCAS.1997.621533
    顯示於類別:[電機工程學系暨研究所] 會議論文


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