A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic

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題名:	A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic
其他題名:	應用低功率電流偵測互補式帶通電晶體邏輯所設計之1.2伏特乘法器
作者:	鄭國興;Cheng, Kuo-hsing;Yee, Liow yu
貢獻者:	淡江大學電機工程學系
日期:	1996-10-13
上傳時間:	2010-04-15 10:48:30 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	This work describes a CMOS 88-bit parallel multiplier for 1.2 V supply voltage. The low-power current-sensing complementary pass-transistor logic (LCSCPTL) is applied to the design of the parallel multiplier. The LCSCPTL have certain advantages in both speed and power dissipation over the CPL circuit. The 4-2 compressors and the conditional carry selection scheme are used in this design to achieve regular layout and improve the operation speed. Moreover, the 1.2 V low-voltage 88-bit parallel multiplier can be designed and fabricated without changing the conventional 5 V 0.8 m CMOS process. Based upon the HSPICE simulation results, the operation speed of the parallel multiplier is 54 ns for 1.2 V supply voltage
關聯:	Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on (Volume:2 ), pp.1037-1040
DOI:	10.1109/ICECS.1996.584564
顯示於類別:	[電機工程學系暨研究所] 會議論文

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