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    題名: A difference detector PFD for low jitter PLL
    作者: 鄭國興;Cheng, Kuo-hsing;Yao, Tse-hua;Jiang, Shu-yu;Yang, Wei-bin
    貢獻者: 淡江大學電機工程學系
    日期: 2001-09
    上傳時間: 2010-04-15 11:32:18 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: For high speed and low jitter PLL application, a new phase frequency detector (PFD) with difference detector is proposed. Because the proposed difference detector PFD (dd-PFD) doesn't have any feedback path in phase frequency detector circuit, it can be operated up to 1.6 GHz. Furthermore, with difference detector, the dd-PFD has three states, so it will not have phase errors and jitter problems. The dead zone of dd-PFD is 16 ps. The proposed PFD is designed using 0.35 μm CMOS technology at 3.3 V power supply.
    關聯: Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on (Volume:1 ), pp.43-46
    DOI: 10.1109/ICECS.2001.957660
    顯示於類別:[電機工程學系暨研究所] 會議論文


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