A low-power high driving ability voltage control oscillator used in PLL

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/38859

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题名:	A low-power high driving ability voltage control oscillator used in PLL
作者:	鄭國興;Cheng, Kuo-hsing;Yang, Wei-bin;Chung, Chun-fu
贡献者:	淡江大學電機工程學系
日期:	2001-05-06
上传时间:	2010-04-15 11:39:11 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal's rise time and fall time rather than on the buffer's delay time. For these applications we propose a novel voltage controlled oscillator (VCO) with split path CMOS driver. It can be proposed to reduce the total power consumption and phase errors of the PLL. The proposed VCO with the split-path CMOS driver has low power consumption and lower area requirement than that achievable by the traditional tapered CMOS buffer.
關聯:	Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Volume:4 ), pp.614-617
DOI:	10.1109/ISCAS.2001.922312
显示于类别:	[電機工程學系暨研究所] 會議論文

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