English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 56401/90256 (62%)
造訪人次 : 11690807      線上人數 : 29
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38857

    題名: The suggestion for CFS CMOS buffer
    作者: Cheng, Kuo-hsing;Yang, Wei-bin
    貢獻者: 淡江大學電機工程學系
    日期: 1999-09-05
    上傳時間: 2010-04-15 11:43:46 (UTC+8)
    出版者: N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
    摘要: Two recent papers, one by Huang et al. (1996) and the other by Cheng et al. (1997), on the driver buffer are commented on. The feedback-controlled split-path CMOS buffer (FS) claims that the 4-split-path buffer can reduce the power and power-delay product. But the voltage of the gates in the output inverter stage is not enough to turn-off the PMOS transistor and the NMOS transistor. Due to this, charge-recovery must be used. The charge-transfer feedback-controlled split-path (CFS) CMOS buffer that has high-speed low-power performance by using transfer of the charge stored in the split output-stage driver to the output node. Thus the power-delay product can be reduced greatly by combining the technology described in the former two papers. The HSPICE simulation results show that the power-delay product of the suggested CMOS buffer is reduced by 20% to 40% in comparison to the conventional CMOS tapered buffer at 100 MHz operation frequency at heavy capacitive load
    關聯: Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on (Volume:2 ), pp.799-802
    DOI: 10.1109/ICECS.1999.813229
    顯示於類別:[電機工程學系暨研究所] 會議論文


    檔案 描述 大小格式瀏覽次數
    The suggestion for CFS CMOS buffer.pdf307KbAdobe PDF219檢視/開啟



    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋