N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
摘要:
Two recent papers, one by Huang et al. (1996) and the other by Cheng et al. (1997), on the driver buffer are commented on. The feedback-controlled split-path CMOS buffer (FS) claims that the 4-split-path buffer can reduce the power and power-delay product. But the voltage of the gates in the output inverter stage is not enough to turn-off the PMOS transistor and the NMOS transistor. Due to this, charge-recovery must be used. The charge-transfer feedback-controlled split-path (CFS) CMOS buffer that has high-speed low-power performance by using transfer of the charge stored in the split output-stage driver to the output node. Thus the power-delay product can be reduced greatly by combining the technology described in the former two papers. The HSPICE simulation results show that the power-delay product of the suggested CMOS buffer is reduced by 20% to 40% in comparison to the conventional CMOS tapered buffer at 100 MHz operation frequency at heavy capacitive load
關聯:
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on (Volume:2 ), pp.799-802
