The charge-transfer feedback-controlled split-path CMOS buffer

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Title:	The charge-transfer feedback-controlled split-path CMOS buffer
Authors:	Cheng, Kuo-hsing;Yang, Wei-bin;Huang, Hong-yi
Contributors:	淡江大學電機工程學系
Date:	1999-03
Issue Date:	2010-04-15 11:10:22 (UTC+8)
Publisher:	New York: Institute of Electrical and Electronics Engineers (IEEE)
Abstract:	Abstract—A new low-power high-speed CMOS buffer, called the charge-transfer feedback-controlled split-path (CFS) CMOS buffer, is proposed. By using the feedback-controlled split-path method, the shortcircuit current of the output inverter is eliminated. Four additional MOS transistors are used as the charge-transfer diodes, which can transfer the charge stored in the split output-stage driver to the output node. Thus the propagation delay and power dissipation of the CFS buffer are reduced. The HSPICE simulation results show that the power-delay product of the CFS CMOS buffer is a savings over 20% in comparison to a conventional CMOS tapper buffer at 100 MHz operation frequency.
Relation:	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46(3), pp.346-348
DOI:	10.1109/82.754867
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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