A low-jitter and low-power phase-locked loop design

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題名:	A low-jitter and low-power phase-locked loop design
作者:	鄭國興;Cheng, Kuo-hsing;Liao, Huan-sen;Tzou, Lin-jiunn
貢獻者:	淡江大學電機工程學系
日期:	2000
上傳時間:	2010-04-15 11:41:45 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	This paper describes a design of digital phase-locked loop (DPLL), which has low-power consumption and low jitter features. A novel voltage controlled oscillator (VCO) and Phase-Frequency Detector (PFD) are proposed to reduce the total power consumption and phase error of the DPLL. The proposed VCO has low power consumption, and the PFD is a “three-state” structure with a dead zone of 5 ps. The power consumption of the proposed DPLL is lower than 6.7 mW, and the output-frequency range of the oscillator is from 200 MHz to 650 MHz. The worst-case cycle jitter is lower than 160 ps, and long-term jitter is lower than 220 ps. We confirm the results based on 0.5 μm CMOS technology and 3 V supply voltage.
關聯:	Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on (Volume:2 ), pp.257-260
DOI:	10.1109/ISCAS.2000.856310
顯示於類別:	[電機工程學系暨研究所] 會議論文

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