English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 55025/89277 (62%)
造访人次 : 10606639      在线人数 : 24
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜寻范围 查询小技巧:
  • 您可在西文检索词汇前后加上"双引号",以获取较精准的检索结果
  • 若欲以作者姓名搜寻,建议至进阶搜寻限定作者字段,可获得较完整数据
  • 进阶搜寻

    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38851

    题名: A low-jitter and low-power phase-locked loop design
    作者: 鄭國興;Cheng, Kuo-hsing;Liao, Huan-sen;Tzou, Lin-jiunn
    贡献者: 淡江大學電機工程學系
    日期: 2000
    上传时间: 2010-04-15 11:41:45 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: This paper describes a design of digital phase-locked loop (DPLL), which has low-power consumption and low jitter features. A novel voltage controlled oscillator (VCO) and Phase-Frequency Detector (PFD) are proposed to reduce the total power consumption and phase error of the DPLL. The proposed VCO has low power consumption, and the PFD is a “three-state” structure with a dead zone of 5 ps. The power consumption of the proposed DPLL is lower than 6.7 mW, and the output-frequency range of the oscillator is from 200 MHz to 650 MHz. The worst-case cycle jitter is lower than 160 ps, and long-term jitter is lower than 220 ps. We confirm the results based on 0.5 μm CMOS technology and 3 V supply voltage.
    關聯: Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on (Volume:2 ), pp.257-260
    DOI: 10.1109/ISCAS.2000.856310
    显示于类别:[電機工程學系暨研究所] 會議論文


    档案 描述 大小格式浏览次数
    0780354826_2p257-260.pdf361KbAdobe PDF647检视/开启



    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回馈