The Design and implementation of DCT/IDCT Chip with Novel Architecture

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Title:	The Design and implementation of DCT/IDCT Chip with Novel Architecture
Authors:	鄭國興;Cheng, Kuo-hsing;Huang, Chih-sheng;Lin, Chun-pin
Contributors:	淡江大學電機工程學系
Date:	2000-05
Issue Date:	2010-04-15 11:42:35 (UTC+8)
Publisher:	N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
Abstract:	In the paper, an efficient VLSI architecture for a 8×8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes sure all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 μm standard cell library and 1P3M CMOS technology, and it can be operated up to 100 MHz
Relation:	Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on (Volume:4 ), pp.741-744
DOI:	10.1109/ISCAS.2000.858858
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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