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    題名: A 1.2 V 500 MHz 32-bit carry-lookahead adder
    作者: 鄭國興;Cheng, Kuo-hsing;Lee, Wen-shiuan;Huang, Yung-chong
    貢獻者: 淡江大學電機工程學系
    日期: 2001-09
    上傳時間: 2010-04-15 11:33:28 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: In this paper a 1.2 V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase-Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-full swing, its operation speed would be higher than the conventional TSPC. Moreover, the supply voltage for the new adder is 1.2 V, thus the power dissipation would also be reduced. The 32-bit CLA adder using 0.35 μm 1P4M CMOS technology with 1.2 V power supply could be operated at a 500 MHz clock frequency.
    關聯: Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on (Volume:2 ), pp.765-768
    DOI: 10.1109/ICECS.2001.957587
    顯示於類別:[電機工程學系暨研究所] 會議論文


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