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    題名: The non-full voltage swing TSPC (NSTSPC) logic design
    作者: Cheng, Kuo-hsing;Huang, Yung-chong
    貢獻者: 淡江大學電機工程學系
    日期: 2000
    上傳時間: 2010-04-15 11:39:47 (UTC+8)
    出版者: N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
    摘要: In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 μm CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage
    In this paper, a new TSPC logic circuit is proposed for low-voltage high-speed applications. The proposed new circuit using non-full voltage swing scheme in internal nodes to reduce logic evaluation time and to save dynamic power. Thus the advantages of the new TSPC logic circuit over the conventional TSPC logic circuit are speed and power-delay product. Based upon the 0.35 μm CMOS technology, the proposed new TSPC logic has 25% improvement over the conventional TSPC circuit in power-delay product. The new circuit can be operated at 250 MHz with 1.2 V supply voltage.
    關聯: ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on, pp.37-40
    DOI: 10.1109/APASIC.2000.896902
    顯示於類別:[電機工程學系暨研究所] 會議論文

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