The novel efficient design of XOR/XNOR function for adder applications

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Proceeding > Item 987654321/38842

Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/38842

Title:	The novel efficient design of XOR/XNOR function for adder applications
Authors:	Cheng, Kuo-hsing;Huang, Chih-sheng
Contributors:	淡江大學電機工程學系
Date:	1999-09-05
Issue Date:	2010-04-15 11:43:27 (UTC+8)
Publisher:	N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
Abstract:	A new concept to implement high performance XOR/XNOR functions that using the pass transistor technique is proposed. It requires only six MOS transistors. Base upon this concept, a new high-speed full adder is proposed for low-power application. We used the modified Karnaugh map (K-map) method to obtain the various pass transistor circuits. We modified the Boolean expression to simplify the control and input signals of the pass transistor logic (PTL) to realize a one-bit full adder. The analysis of the proposed one-bit adders is compared with that of the static CMOS adder, the CPL transmission function adder, the DPL transmission gate adder, and the CPL transmission gate adder. The simulation results shows that the proposed new circuit has the lowest power delay product performance
Relation:	Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on (Volume:1 ), pp.29-32
DOI:	10.1109/ICECS.1999.812216
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	344	View/Open
The novel efficient design of XOR XNOR function for adder applications.pdf		261Kb	Adobe PDF	244	View/Open