N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
摘要:
A new concept to implement high performance XOR/XNOR functions that using the pass transistor technique is proposed. It requires only six MOS transistors. Base upon this concept, a new high-speed full adder is proposed for low-power application. We used the modified Karnaugh map (K-map) method to obtain the various pass transistor circuits. We modified the Boolean expression to simplify the control and input signals of the pass transistor logic (PTL) to realize a one-bit full adder. The analysis of the proposed one-bit adders is compared with that of the static CMOS adder, the CPL transmission function adder, the DPL transmission gate adder, and the CPL transmission gate adder. The simulation results shows that the proposed new circuit has the lowest power delay product performance
關聯:
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on (Volume:1 ), pp.29-32
