High efficient 3-input XOR for low-voltage low-power high-speed applications

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/38841

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題名:	High efficient 3-input XOR for low-voltage low-power high-speed applications
作者:	Cheng, Kuo-hsing;Hsieh, Ven-chieh
貢獻者:	淡江大學電機工程學系
日期:	1999
上傳時間:	2010-04-15 11:44:07 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.
關聯:	ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on, pp.166-169
DOI:	10.1109/APASIC.1999.824054
顯示於類別:	[電機工程學系暨研究所] 會議論文

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