English  |  正體中文  |  简体中文  |  Items with full text/Total items : 55176/89445 (62%)
Visitors : 10659206      Online Users : 29
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38841

    Title: High efficient 3-input XOR for low-voltage low-power high-speed applications
    Authors: Cheng, Kuo-hsing;Hsieh, Ven-chieh
    Contributors: 淡江大學電機工程學系
    Date: 1999
    Issue Date: 2010-04-15 11:44:07 (UTC+8)
    Publisher: Institute of Electrical and Electronics Engineers (IEEE)
    Abstract: A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.
    Relation: ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on, pp.166-169
    DOI: 10.1109/APASIC.1999.824054
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

    Files in This Item:

    File Description SizeFormat
    0780357051_p166-169.pdf250KbAdobe PDF5639View/Open

    All items in 機構典藏 are protected by copyright, with all rights reserved.

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback