A new logic synthesis and optimization procedure

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/38840

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题名:	A new logic synthesis and optimization procedure
作者:	鄭國興;Cheng, Kuo-hsing;Hsieh, Ven-chieh
贡献者:	淡江大學電機工程學系
日期:	2001-05-06
上传时间:	2010-04-15 11:38:53 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.
關聯:	Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Volume:4 ), pp.182-185
DOI:	10.1109/ISCAS.2001.922202
显示于类别:	[電機工程學系暨研究所] 會議論文

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