English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 59169/92571 (64%)
造访人次 : 748115      在线人数 : 50
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜寻范围 查询小技巧:
  • 您可在西文检索词汇前后加上"双引号",以获取较精准的检索结果
  • 若欲以作者姓名搜寻,建议至进阶搜寻限定作者字段,可获得较完整数据
  • 进阶搜寻


    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38840


    题名: A new logic synthesis and optimization procedure
    作者: 鄭國興;Cheng, Kuo-hsing;Hsieh, Ven-chieh
    贡献者: 淡江大學電機工程學系
    日期: 2001-05-06
    上传时间: 2010-04-15 11:38:53 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.
    關聯: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Volume:4 ), pp.182-185
    DOI: 10.1109/ISCAS.2001.922202
    显示于类别:[電機工程學系暨研究所] 會議論文

    文件中的档案:

    档案 描述 大小格式浏览次数
    0780366859_4p182-185.pdf347KbAdobe PDF474检视/开启
    index.html0KbHTML203检视/开启

    在機構典藏中所有的数据项都受到原著作权保护.

    TAIR相关文章

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回馈