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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38840


    Title: A new logic synthesis and optimization procedure
    Authors: 鄭國興;Cheng, Kuo-hsing;Hsieh, Ven-chieh
    Contributors: 淡江大學電機工程學系
    Date: 2001-05-06
    Issue Date: 2010-04-15 11:38:53 (UTC+8)
    Publisher: Institute of Electrical and Electronics Engineers (IEEE)
    Abstract: The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.
    Relation: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Volume:4 ), pp.182-185
    DOI: 10.1109/ISCAS.2001.922202
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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