English  |  正體中文  |  简体中文  |  Items with full text/Total items : 57042/90725 (63%)
Visitors : 12437900      Online Users : 69
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38840

    Title: A new logic synthesis and optimization procedure
    Authors: 鄭國興;Cheng, Kuo-hsing;Hsieh, Ven-chieh
    Contributors: 淡江大學電機工程學系
    Date: 2001-05-06
    Issue Date: 2010-04-15 11:38:53 (UTC+8)
    Publisher: Institute of Electrical and Electronics Engineers (IEEE)
    Abstract: The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.
    Relation: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Volume:4 ), pp.182-185
    DOI: 10.1109/ISCAS.2001.922202
    Appears in Collections:[電機工程學系暨研究所] 會議論文

    Files in This Item:

    File Description SizeFormat
    0780366859_4p182-185.pdf347KbAdobe PDF458View/Open

    All items in 機構典藏 are protected by copyright, with all rights reserved.

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback