Institute of Electrical and Electronics Engineers (IEEE)
The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on (Volume:4 ), pp.182-185