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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38838


    Title: The Improvement of Conditional Sum Adder for Low Power Applications
    Authors: 鄭國興;Cheng, Kuo-hsing;Chiang, Shu-min;Cheng, Shun-wen
    Contributors: 淡江大學電機工程學系
    Date: 1998-09-13
    Issue Date: 2010-04-15 11:08:58 (UTC+8)
    Publisher: Piscataway: Institute of Electrical and Electronics Engineers
    Abstract: The authors describe a new conditional-sum rule for low power applications. This conditional sum adder is especially attractive for implementing high-speed arithmetic systems. The new conditional sum addition rule can reduce the internal nodes and multiplexer numbers of the adder design. Various supply voltages and circuit structures are used to implement the new conditional sum adders. It is shown that about 10% to 25% power-delay product is saved
    Relation: ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International, pp.131-134
    DOI: 10.1109/ASIC.1998.722817
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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