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    题名: The Improvement of Conditional Sum Adder for Low Power Applications
    作者: 鄭國興;Cheng, Kuo-hsing;Chiang, Shu-min;Cheng, Shun-wen
    贡献者: 淡江大學電機工程學系
    日期: 1998-09-13
    上传时间: 2010-04-15 11:08:58 (UTC+8)
    出版者: Piscataway: Institute of Electrical and Electronics Engineers
    摘要: The authors describe a new conditional-sum rule for low power applications. This conditional sum adder is especially attractive for implementing high-speed arithmetic systems. The new conditional sum addition rule can reduce the internal nodes and multiplexer numbers of the adder design. Various supply voltages and circuit structures are used to implement the new conditional sum adders. It is shown that about 10% to 25% power-delay product is saved
    關聯: ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International, pp.131-134
    DOI: 10.1109/ASIC.1998.722817
    显示于类别:[電機工程學系暨研究所] 會議論文


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