Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization

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題名:	Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization
作者:	Cheng, Kuo-hsing;Cheng, Shun-wen
貢獻者:	淡江大學電機工程學系
日期:	2002-01-07
上傳時間:	2010-01-11 16:01:16 (UTC+8)
出版者:	N.Y.: IEEE (Institute of Electrical and Electronic Engineers)
摘要:	Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: "does any rule exist that contains all good?" This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and is suitable for low supply voltage. It has full swing signal in all nodes and high robustness against transistor downsizing and voltage scaling
關聯:	Proc. Joint ASP-DAC and Int'l VLSI design, ASPDAC 2002, Banglore, pp.155-159
DOI:	10.1109/ASPDAC.2002.994909
顯示於類別:	[電機工程學系暨研究所] 會議論文

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