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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38833


    Title: A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency
    Authors: 鄭國興;Cheng, Kuo-hsing;Chen, Yu-jung
    Contributors: 淡江大學電機工程學系
    Date: 2001-09
    Issue Date: 2010-04-15 11:25:35 (UTC+8)
    Publisher: Institute of Electrical and Electronics Engineers (IEEE)
    Abstract: In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block A new binary search decision scheme was used to accelerate the frequency acquisition process. It can reduce the chip area and increase the operating frequency. In this design, a 14-bit control word is used to control the digital control oscillator. The new type ADPLL has been designed and implemented by TSMC's 0-35 μ IP4M CMOS process for 3.3V applications. The phase lock process takes 20-reference cycle, and the maximum frequency of the proposed ADPLL is about 820MHz.
    Relation: ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International, pp.139-143
    DOI: 10.1109/ASIC.2001.954687
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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