A 10-bit 2.5 mW 0.27 mm2 CMOS DAC with spike-free switching

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Title:	A 10-bit 2.5 mW 0.27 mm2 CMOS DAC with spike-free switching
Authors:	郭建宏;Kuo, Chien-hung;Tsai, Jen-chieh
Contributors:	淡江大學電機工程學系
Date:	2005-06-14
Issue Date:	2010-04-15 11:12:28 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers (IEEE)
Abstract:	A low-power digital-to-analog converter for portable electronics is introduced A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18 μm 1P6M CMOS standard technology, and its core area is 0.27 mm2. The simulation results show the DNL/INL is ±0.14/0.14 at a conversion rate of 10 MHz, and consume 2.5 mW of power from a 1.8 V supply voltage.
Relation:	Consumer Electronics, 2005. (ISCE 2005). Proceedings of the Ninth International Symposium on, pp.473-477
DOI:	10.1109/ISCE.2005.1502426
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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