Institute of Electrical and Electronics Engineers (IEEE)
摘要:
A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time and nonidealities on PFD/CP. This PLL utilizes a tunable delay cell to reduce the ripple on the VCO control line and hence the jitter penalty. In addition, a fully differential delay cell for voltage-controlled oscillator (VCO) is introduced to perform a wide locking range and low-jitter performance. The proposed PLL was implemented in 0.35-μm 2P4M CMOS standard technology with the core area of 0.1mm. It can be operated from 250MHz to 1.29GHz and consume 38.2mW of power at 1GHz under a 3.3-V supply voltage.
關聯:
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (Volume:3 ), pp.2799-2802
