English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 58210/91779 (63%)
造訪人次 : 13776089      線上人數 : 44
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38671

    題名: A Novel Loop Filter Design for Phase-Locked Loops
    作者: 周永山;Chou, Yung-shan;Mao, W. L.;Chen, Y. C.;Chang, F. R.
    貢獻者: 淡江大學電機工程學系
    日期: 2006-10-08
    上傳時間: 2010-04-15 11:08:41 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: A new loop filter design method for phase locked loops (PLLs) is presented, which employs multi-objective control technique to deal with the various design objectives: small noise bandwidth, good transient response (small settling time, small overshoot), and large gain and phase margins. Trade-off among the conflicting objectives is made via recently developed convex optimization skill in conjunction with appropriate adjustment of certain design parameters. One salient feature of the proposed method is that it allows one to specify the filter poles in advance, including the special case of PI form filter. Moreover, the proposed method is applicable to PLL of any order. Numerical simulation on nonlinear PLL model is performed which demonstrates the effectiveness of the proposed method.
    關聯: Systems, Man and Cybernetics, 2006. SMC '06. IEEE International Conference on (Volume:4 ), pp.2932-2938
    DOI: 10.1109/ICSMC.2006.384563
    顯示於類別:[電機工程學系暨研究所] 會議論文


    檔案 描述 大小格式瀏覽次數
    1424400996_4p2932-2938.pdf1102KbAdobe PDF2295檢視/開啟



    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋