Institute of Electrical and Electronics Engineers (IEEE)
摘要:
In this paper, we propose the architecture of a CMOS fully integrated level-locked loop (LLL). A 455 kHz LLL without external reference signal achieves the target of 1 percent variation, and consumes 9 mW with 3.6 V power supply in a standard 0.5 μm CMOS process. The frequency-to-voltage converter (FVC) in the LLL, built upon the charge redistribution principle, can decrease the process variation. A programmable controller is developed to increase the frequency accuracy. The voltage-controlled oscillator (VCO) is based on differential delay cells in order to minimize the effect of the power supply and the substrate noise. According to the main circuits, operated at 1.8 V provided by a regulator, the output frequency is accurately for 455 kHz from 2.0 V to 3.6 V.
關聯:
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on, pp.197-200
