A new robust handshake for asymmetric asynchronous micro-pipelines

doi:10.1109/ISCAS.2003.1206233

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Title:	A new robust handshake for asymmetric asynchronous micro-pipelines
Authors:	Cheng, Kuo-hsing;李揚漢;Lee, Yang-han;Chang, Wei-chun
Contributors:	淡江大學電機工程學系
Date:	2003-05-25
Issue Date:	2010-04-15 11:15:30 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers (IEEE)
Abstract:	In this paper, a new handshake methodology to enhance the performance of the asynchronous micro-pipeline systems is proposed. The proposed handshake methodology has more flexibilities to design an asymmetric asynchronous micro-pipeline system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. Others, the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. An asynchronous micro-pipeline array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35μm CMOS technology, the simulation results show that the proposed new handshake methodology has shortest latency and more robust property as compare with other handshake methodologies.
Relation:	Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on (Volume:5 ), pp.209-212
DOI:	10.1109/ISCAS.2003.1206233
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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