N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
摘要:
Division operation is very important in computer systems. Conventionally synchronous techniques are applied to implement the divider. In this paper we propose a new asynchronous architecture for the divider. In this asynchronous scheme, the architecture is simple and is very easy to implement in VLSI. With this asynchronous architecture, we use TSMC's 0.6 um SPDM process to design a 32-b/32-b radix-2 non-restoring divider. The HSPICE simulation shows that this divider can finish a 32-b/32-b division operation in 3.7 ns to 160.2 ns
關聯:
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on (Volume:2 ), pp.173-176
