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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38565

    Title: The design and implementation of an asynchronous radix-2 non-restoring 32-b/32-b ring divider, 2, pp.173-176
    Authors: Chiang, Jen-shiun;Liao, Jun-yao
    Contributors: 淡江大學電機工程學系
    Date: 1998-05-31
    Issue Date: 2010-04-15 10:52:25 (UTC+8)
    Publisher: N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
    Abstract: Division operation is very important in computer systems. Conventionally synchronous techniques are applied to implement the divider. In this paper we propose a new asynchronous architecture for the divider. In this asynchronous scheme, the architecture is simple and is very easy to implement in VLSI. With this asynchronous architecture, we use TSMC's 0.6 um SPDM process to design a 32-b/32-b radix-2 non-restoring divider. The HSPICE simulation shows that this divider can finish a 32-b/32-b division operation in 3.7 ns to 160.2 ns
    Relation: Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on (Volume:2 ), pp.173-176
    DOI: 10.1109/ISCAS.1998.706869
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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