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    題名: A novel asynchronous control unit and the application to a pipelined multiplier
    作者: 江正雄;Chiang, Jen-shiun;Liao, Jun-yao
    貢獻者: 淡江大學電機工程學系
    日期: 1998-05-31
    上傳時間: 2010-04-15 10:50:54 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: This paper discusses the technique for asynchronous circuit design using a novel asynchronous control unit. We employ the very commonly used device, pass-transistor multiplexer, to design and implement the asynchronous control unit. Even though the architecture of the control unit is simple, the efficiency is good. A multiplier with pipelined structure has been designed to verify the usefulness of this technique. We use TSMC's 0.6 μm SPDM process to design and implement an 8-b×8-b pipelined multiplier. The HSPICE simulation shows that the feedthrough rate of the inputs can be as high as 250 MHz.
    關聯: Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on (Volume:2 ), pp.169-172
    DOI: 10.1109/ISCAS.1998.706868
    顯示於類別:[電機工程學系暨研究所] 會議論文


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